C068 - A single MS gate is calibrated with detuning delta = 2 pi x 14.7 kHz; slow ramping gives...
Verdict: partial
Location: Supp. Mat. S5
Type / expected artifact: numeric / numeric
Claim: A single MS gate is calibrated with detuning delta = 2 pi x 14.7 kHz; slow ramping gives a total gate time t = 75 us, longer than 2 pi/delta = 68 us.
Models: extraction claude-opus-4-8; verification gpt-5; verification_chain claude-opus-4-8 -> gpt-5; verdict_chain partial -> partial.
Limitations: paper_text_only_reimplementation.
Source location(s): source/supp_content.tex:133 (Supp. Mat. S5).
Conclusion
Paper: delta=2pi*14.7kHz -> 2pi/delta=68us; ramped gate t=75us>68us. The 2pi/delta value is a pure identity computing to 68.03us, matching the stated 68us to 0.04%. The 75us is a calibrated ramped gate time (paper-reported, not derivable); only the inequality 75>68 is asserted and it holds. The derivable part is exact but the 75us is paper_text_only -> partial.
Verification details
Executable rerun: run.py exited 0 in 0.417s; log verification/C068/attempts/R002/run.log.
Output excerpt:
2 pi / delta = 68.027 us (paper states 68 us)
paper ramped gate time t = 75 us
75 us > 68.0 us ? True
relative error on 68us claim: 0.04%